1. Field of the Invention
The present invention relates to semiconductor integrated circuits and more particularly to a semiconductor integrated circuit in which a product between analogue signals is evaluated and the result of the evaluation is converted to a digital code and outputted.
2. Description of the Prior Art
According to recent developments in digital integrated circuits, there is an increasing demand for digital signal processing for purposes of enhancing performance, integration scales and capabilities even in technical fields in which signal processing was performed in analogue circuits. For example, in order to process, in a digital manner, voice, images and the like which are inherently analogue signals, an analogue-to-digital (A/D) converter is indispensably required.
FIGS. 4A to 4C are block diagrams of various modulation systems in conventional analogue circuits. The constructions shown in FIGS. 4A to 4C are shown for example in "Modern Electrical Communications Theory and Systems" by H. Stark et al., page 325. FIG. 4A shows an amplitude modulation system, FIG. 4B shows a phase modulation system, and FIG. 4C shows a frequency modulation system. In each of those three systems, it is necessary to obtain the product of two analogue signals, i.e., an input signal S(t) and a carrier wave (cos .omega..sub.c t or sin .omega..sub.c t case, two methods as shown in FIGS. 5A and 5B are considered as to in which part of the circuit an A/D converter for converting an analogue signal to digital data is to be provided.
FIG. 5A shows a method in which the product of the analogue signals in each of the modulation systems shown in FIGS. 4A to 4C is obtained by an analogue multiplier and the product output is converted to digital data by the A/D converter. FIG. 5B shows another method in which one of the analogue signals is converted to digital data and the other analogue signal is obtained as digital data by reading out data from a ROM table where data has been written in a digitally converted form, whereby those digital data are multiplied by a digital multiplier.
FIG. 6 is a diagram showing a conventional A/D converter of a parallel comparison system described for example in "Monolithic Expandable 6-bit 20 MHz CMOS/SOS A/D Converter" by A. Dingwall, IEEE, Journal of Solid State Circuits, Vol. SC-14, No. 6, Dec. 1979, pp. 926-932. Referring to FIG. 6, the A/D converter comprises a reference voltage terminal 1, an analogue input terminal 2, ladder resistors 3, comparators 4 arranged in parallel, an encoding circuit 5, and digital output terminals 6. The ladder resistors 3 define reference voltages of the respective comparators 4.
Now, operations of the A/D converter shown in FIG. 6 will be described. A voltage applied to the reference voltage terminal 1 is divided on resistance by the ladder resistors 3 so as to be received by an input terminal of each of the comparators 4. Each comparator 4 compares the reference voltage applied to the input terminal and a signal applied to the analogue input terminal 2 and outputs the result of the comparison. The outputs of the comparators 4 are coded by the encoding circuit 5 and the outputs thus coded appear as digital data at the output terminals 6. If the outputs are N bits, the number of comparators required is 2.sup.N -1.
Details of the A/D converter shown in FIG. 6 will be described with reference to concrete examples shown in FIGS. 7 and 8. FIG. 7 shows an A/D converter of a parallel comparison system of 3-bit straight binary code output. FIG. 8(a) and FIG. 8(b) show an example of a comparator output and an example of an encoded output, respectively, in the A/D converter shown in FIG. 7. Since this A/D converter is of the parallel comparison system, the outputs of the comparators 4 are all "1" (at high level) or "0" (at low level), or they are outputs where only one change point exists between the outputs "1" and the outputs "0", in the well known thermometer code representation. More specifically, the number of the contiguous outputs "1" out of the outputs of the respective comparators 4 corresponds to the value of the analogue input. In the case of FIG. 7, since a logic boundary exists between the terminals 4b and 4c, the number of the contiguous outputs "1" is five and this means that the value of the analogue input is "5". If the encoding portion 5 for the above described outputs of the comparators has a construction as shown in FIG. 7, the encoded output (the most significant bit being provided at a terminal 6a) is a binary code "5"(101) for the output "5" of the comparison.
If a product output between two analogue signals is obtained by conversion to digital data in the system shown in FIG. 5A or FIG. 5B by using the A/D converter of the parallel comparison system shown in FIGS. 6 and 7, the following disadvantages are involved.
First, in the system of FIG. 5A, two analogue input signals are multiplied by using an analogue multiplier; however, the analogue multiplier does not have a good precision. In addition, if the result of the multiplication of the analogue multiplier is to be converted to digital data by the A/D converter, the number of bits required in the A/D converter is twice larger than that in the case of FIG. 5B. As a result, a circuit area of the A/D converter is increased and the precision of the A/C converter is lowered. Furthermore, a considerable difficultly is involved in manufacturing the A/D converter.
On the other hand, in the system of FIG. 5B, two A/D converters are required (the ROM is also a kind of an A/D converter). Accordingly, a circuit configuration is complicated and requires a large size and the manufacturing cost comes to be high. In addition, although a digital multiplier is used for multiplication in the case of FIG. 5B, the digital multiplier has a complicated circuit configuration and a large size and it also has a disadvantage such as a slow processing speed due to a delay in transmission.